1. Field of the Invention
The present invention relates to a light emission array head, a method of adjusting a driving level of a driving signal for this head, and an image formation apparatus. In particular, the present invention relates to a light emission array head which is used as a recording light emission element to form a permanent visible image on a recording medium by an electrophotographic recording system, a method of adjusting a driving level of a driving signal for the light emission array head, and an image formation apparatus which contains the light emission array head.
2. Related Background Art
Conventionally, a self-scanning type LED (light emitting diode) array (called an SLED hereinafter) has been introduced in Japanese Patent Application Laid-Open Nos. 1-238962, 2-208067, 2-212170, 3-194978, 4-5872, 4-23367, 4-296579 and 5-84971, Japan Hard-copy Memoir 1991 (A-17)xe2x80x9cProposal of Light Emission Element Array for Light Printer in Which Driving Circuits Have Been Integratedxe2x80x9d, IEICE (Institute of Electronics, Information and Communication Engineers) Memoir (Mar. 5, 1990)xe2x80x9cProposal of Self-Scanning Type Light Emission Element (SLED) Using PNPN Thristor Structurexe2x80x9d, and the like. Thus, the SLED has been paid attention to as a recording light emission element (i.e., a light emission element used for image recording) for an image formation apparatus of an electrophotographic system.
FIG. 5 shows an example of this SLED. An operation of this SLED will be explained with reference to FIG. 5.
As shown in FIG. 5, the SLED is composed of transfer thyristors (i.e., thyristors used for data transfer) ST1 to ST5 which are cascaded and light emission thyristors (i.e., thyristors used for light emission) SL1 to SL5 which are cascaded. As shown in FIG. 5, gate signals of the respective thyristors are set to be common. The gates of the first thyristors SL1 and ST1 are connected to the input part of a signal "PHgr"S, the gates of the second thyristors SL2 and ST2 are connected to the cathode of a diode connected to the terminal of the signal "PHgr"S, and the gates of the third thyristors SL3 and ST3 are connected to the cathode of a next diode.
FIGS. 6A to 6F are timing charts showing control signals of the SLED and on/off states of the thyristors. Further, FIGS. 6A to 6F show an example that all elements are lit. Hereinafter, the data transfer and the light emission will be explained according to the timing charts shown in FIGS. 6A to 6F.
The data transfer is started by changing the level of the signal "PHgr"S (FIG. 6A) from 0V to 5V. When the level of the signal "PHgr"S reaches 5V, a voltage Va=5V, a voltage Vb=3.7V (it is assumed that forward voltage drop of the diode is 1.3V), a voltage Vc=2.4V, a voltage Vd=1.1V, and a voltage Ve and following=0V. Further, the gate voltage of the transfer thyristor ST1 is changed from 0V to 5V, and the gate voltage of the transfer thyristor ST2 is changed from 0V to 3.7V, and the gate voltages of the following thyristors are changed similarly.
In this state, by changing the level of a signal "PHgr"1 (FIG. 6B) from 5V to 0V, potentials of the anode, cathode and gate of the transfer thyristor ST1 become 5V, 0V and 3.7V respectively, thereby satisfying an on condition of this thyristor. When the transfer thyristor ST1 is turned on, this thyristor ST1 is still in the on state even if the level of the signal "PHgr"S is changed to 0V, thereby maintaining the voltage Va≅5V. This is because the signal "PHgr"S is supplied through a resistor (not shown), and a potential between the anode and gate of the thyristor has substantially the same value when the thyristor is turned on.
Thus, even if the level of the signal "PHgr"S is changed to 0V, the on condition of the first thyristor is maintained, and a first shift operation ends. In this state, when the level of a signal "PHgr"I for the light emission thyristor (FIG. 6D) is changed from 5V to 0V, the condition same as the condition that the transfer thyristor is turned on is satisfied, whereby the light emission thyristor SL1 is turned on, and a first LED is lit. When the level of the signal "PHgr"I is returned to 5V, a potential difference between the anode and cathode of the light emission thyristor becomes zero, and thus a minimum holding current of the thyristor can not be flowed, whereby the light emission thyristor SL1 is turned off.
Next, transfer of the on condition from the transfer thyristor ST1 to the transfer thyristor ST2 will be explained.
Since the level of the signal "PHgr"1 is maintained to 0V even if the light emission thyristor SL1 is turned off, the transfer thyristor ST1 is still on, and the gate voltage of the transfer thyristor ST1 satisfies Va≈5V and Vb=3.7V. In this state, by changing the level of a signal "PHgr"2 (FIG. 6C) from 5V to 0V, potentials of the anode, cathode and gate of the transfer thyristor ST2 become 5V, 0V and 3.7V respectively, whereby the transfer thyristor ST2 is turned on. After the transfer thyristor ST2 has been turned on, when the level of the signal "PHgr"1 is changed from 0V to 5V, the transfer thyristor is turned off similarly to turning off of the light emission thyristor SL1.
Thus, the on condition is shifted from the transfer thyristor ST1 to the transfer thyristor ST2. Then, when the level of the signal "PHgr"I is changed from 5V to 0V, the light emission thyristor SL1 is turned on, and the LED is lit. The reason why only the light emission thyristor corresponding to the transfer thyristor being on can emit the light is as follows. Namely, when the transfer thyristor is not on, since the gate voltages of the thyristors except for the thyristor adjacent to the thyristor being on are 0V, the on condition of the thyristor is not satisfied. With respect to the adjacent thyristor, when the light emission thyristor is turned on, the potential level of the signal "PHgr"I becomes 3.4V (corresponding to forward voltage drop of the light emission thyristor). Thus, since a potential difference between the gate and cathode of the adjacent thyristor is zero, this thyristor can not be turned on.
It was explained in the above description that the light emission thyristor is turned on by shifting the level of the signal "PHgr"I to 0V, whereby the LED is lit. In a practical image formation operation, it is of course necessary to control whether or not the LED is to be actually lit at such timing, in accordance with image data. Image data Dp shown in FIG. 6E and a signal "PHgr"D shown in FIG. 6F represent such control. Namely, the logical sum of the signal "PHgr"I and the image data Dp is obtained externally. Only when the image data Dp is 0V, a "PHgr"I terminal of the SLED actually becomes 0V, whereby the light is emitted. When the image data Dp is 5V, the "PHgr"I terminal of the SLED is maintained to 5V, whereby the light is not emitted.
Next, a packaging state of an SLED array head will be explained with reference to FIG. 7 which illustrates appearance of the head.
SLED semiconductor chips 511 are mounted on a base substrate 512 to which a print wiring board such as a glass epoxy board, a ceramic board or the like is used. A control signal is externally supplied to a lighting control circuit (driver IC) 514, whereby this circuit 514 generates a lighting control signal for the SLED semiconductor chips 511. An external control signal is input from a connector 513, power is input from a power supply circuit 532 through a power supply cable 531, and the input signal and power are supplied to each semiconductor.
Bonding wires 515 are connected to the SLED semiconductor chips 511, whereby the output signals "PHgr"1, "PHgr"2, "PHgr"S and "PHgr"I from the driver IC 514 and negative-electrode-side power (GND in this example) are input through these wires 515. Numeral 516 denotes a positive-electrode-side power supply pattern (+5V in this example) which is drawn on the base substrate 512. Numeral 517 denotes a silver paste which gives electrical conductivity between the positive-electrode-side power supply pattern 516 and a back electrode of the SLED semiconductor chip 511 and firmly adheres the pattern 516 to the chip 511.
The SLED array head which has the above structure and operates as above is used as a light writing device in an image formation apparatus which comprises an image reader unit including a CCD sensor or the like and a printer unit for performing image formation in an electrophotographic system based on image data from the image reader unit. Namely, the image formation apparatus causes an electrifier to primarily electrify a photosensitive drum, causes the SLED array head to form an electrostatic latent image on the photosensitive drum based on the image data, causes a development unit to develop this electrostatic latent image to form a toner image, and causes a transfer unit to transfer the toner image onto a recording medium and output this recording medium.
In such an LED array, the dispersion of light emission quantity causes the dispersion of pixel density. Namely, if there is the dispersion of light emission in each chip of the LED array, it directly influences a pixel density of an output image, thereby causing the dispersion of pixel density. Thus, for example, it is necessary to optimize a driving current of the driving circuit for each light emission thyristor such that a light emission quantity in case of causing each chip to emit light at a predetermined power supply voltage, a predetermined time width and a predetermined light emission control signal pattern comes to be within a predetermined range, thereby controlling the dispersion of light emission quantity to maintain the pixel density to a predetermined value.
Especially, in the SLED, not only the driving current for the light emission element (light emission thyristor) but also a driving current for the transfer thyristor causes an inequable light quantity. This is because, since the light emission thyristor has the semiconductor lamination structure same as that for the transfer thyristor, the transfer thyristor is lit when the light emission thyristor is turned on, and though this transfer thyristor is masked by a metal film there is leakage light in some measure from a space of such a mask.
Such the inequable light quantity due to the leakage light can be controlled by reducing the driving current of the transfer thyristor. However, when the driving current is reduced too much, the on state of the thyristor can not be maintained, whereby there is some fear that a normal transfer operation can not be performed.
Thus, it is possible to use a means for controlling the dispersion of light emission quantity by providing the highly specified LED array chip and driving circuit. However, even in this case, a yield factor is naturally deteriorated when a desired quality of the output image is high. Thus, such the means is undesirable because a manufacturing cost becomes very expensive.
As above, it is necessary to adjust also the driving current for the driving other than the driving of the light emission elements of the LED array, within an appropriate range.
Next, a driving system for adjusting the driving current proposed as above to control the dispersion of light emission quantity of the SLED will be explained. FIG. 8 is a block diagram showing an example of such the conventional driving system.
In FIG. 8, numeral 600 denotes each of SLED array chips, numeral 601 denotes a driving circuit, and numeral 603 denotes each of plural driving current limitation resistors. Incidentally, the plural SLED array chips (56 pieces in this case) are provided. The driving circuit 601 drives these 56 SLED array chips 600. The driving current limitation resistor 603 is provided to the collector of each of driving transistors Q61, Q62, Q63, . . . , in the driving circuit 601. Numeral 652 denotes a control IC, and numeral 602 denotes a DC power supply (+5V). A consumption current detector 604 which is externally connected measures a quantity of the driving currents flowing in the driving current limitation resistors 603.
In case of adjusting the driving current, the resistance of the driving current limitation resistor 603 is set to r1. In this state, a driving current Ir1 of each bit of the SLED array chips 600 is measured. Next, the resistance of the driving current limitation resistor 603 is changed to another value r2. In this state, a driving current Ir2 of each bit of the SLED array chips 600 is measured similarly.
According to such measured results, the values of the driving currents Ir1 and Ir2 to the two kinds of resistances r1 and r2 for each bit are plotted as shown in FIG. 9, and the relation between the resistance and the current is approximated by using the straight line extended between two points, whereby a resistance rx estimated to be able to obtain a desired current quantity Ix is calculated according to the approximation of the straight line.
The measurement and the approximation of the straight line same as those explained above are performed to all the SLED array chips, and the resistor having the calculated resistance rx is mounted as the driving current limitation resistor. Thus, by adjusting the resistance of the driving current limitation resistor, the dispersion of light emission quantity of the SLED array head is controlled within the predetermined range.
Conventionally, as above, the circuit structure to compensate the output current of the driving circuit is externally added for each SLED array chip, whereby the dispersion of light emission quantity among the chips and the dispersion of driving circuit characteristic are flexibly and exactly corrected.
However, in such the conventional structure for compensation, there are quite a lot of numbers n of chips (including the number of light emission elements) especially in a print head, whereby there are a lot of numbers of mounting parts. Thus, it is necessary to prepare many kinds of resistances to perform delicate adjustment, whereby there is a problem of inviting the rise of the execution cost.
Further, in the print head or the like, since the mounting form is high density and minute, also the structure to enable measurement of a driving current (i.e., the structure to shunt at a measurement-desired point) becomes minute, and a minute type is used as for the mounting resistor. In such the form, exchange working of the minute-type resistor is difficult, whereby there is another problem that the exchange working required many times in the above adjustment is extremely difficult and requires a long time.
For example, in a case where the chips of which number n=56 are provided for one device and the resistance of the current limitation resistor corresponding to each chip is adjusted by ten stages, the number of stock parts of the resistors which should be prepared is 560 in simplicity as for one device. Thus, even in this case, the frequency by which the resistor should be exchanged is necessary at least as many as 168 times (i.e., 56 chipsxc3x973 times).
In order to solve the above problems which originates in the exchange of the resistors and to facilitate the adjustment of the device, it is necessary to use the parts such as plural variable resistors or to prepare an expensive head mounting form by needlessly using a large substrate.
The present invention has been made in consideration of the above points, and an object thereof is to provide a light emission array head which solved the above problems, a method of adjusting a driving level of a driving signal for the light emission array head, and an image formation apparatus which contains the light emission array head.
To achieve the object, there is provided a light emission array head in which plural semiconductor chips each containing plural light emission elements arranged in a predetermined direction are arranged in the predetermined direction, and which causes the plural light emission elements of the plural semiconductor chips to emit light in accordance with a predetermined driving signal, the light emission array comprising:
driving means for driving the plural light emission elements in accordance with a predetermined control signal;
control means for generating the predetermined control signal, and controlling the plural semiconductor chips to operate at a predetermined control signal level and light emission pattern; and
one adjustment means for adjusting in common a driving level of the predetermined driving signal by the driving means according to the predetermined control signal,
wherein a consumption current consumed by the control means is subtracted from a total power supply consumption current measurement value in case of causing each of the plural semiconductor chips to perform a predetermined operation in accordance with the predetermined control signal sent from the control means, a driving current value supplied from the driving means to the semiconductor chip is calculated, and the adjustment by the adjustment means is performed, whereby the driving level of the driving signal can be adjusted to be within a predetermined range.